The invention relates to a computer system, comprising
a main bus interconnecting a main memory and at least one control unit, which is for controlling an asscociated peripheral apparatus, PA0 a processor having logic address generating means, and a first memory management control unit for receiving said logic address for conversion into an associated physical address, PA0 communication means for communicating said physical address to said main memory and associated data between said main memory and the processor.
The following description is based specifically on the so-called VME-bus standard which is also generally known as IEC 821 bus and IEEE P1014, details of which are given in the VME-bus Specification Manual, revision C, February 1985, published by the VME-bus Manufacturers Group. As is known, the processor may comprise its own foreground memory, for example a cache memory. The main memory consists of RAM modules, possibly organized in memory banks, and has a capacity of, for example 16 Mbytes. In principle 24 address bits then suffice; the width of the main bus will usually be sufficient for transporting this address in parallel. The 24 bits can represent a logic address as well as a physical address. A physical address directly specifies a given memory location. A logic address comprises, for example a page/segment indication, together with offset information. On this logic address the first memory management control unit performs a conversion operation. When the main memory is composed of dynamic RAM memory modules, it also comprises a refresh organization of some kind. When a given memory location has not been addressed for an excessively long period of time, a refresh access is scheduled. A two-port access element enables the intermingled execution of user accesses and refresh accesses.